Data processing devices can employ multiple clock domains, with logic modules in each domain synchronized to a clock signal associated with that domain. Under normal operating conditions, the clock signals associated with different clock domains can be asynchronous with each other. However, testing a data processing device when clock domains operate asynchronously can be problematic, because if data is transferred between the clock domains during testing, the uncertainty in the timing of the transfer can cause the receiving clock domain to experience transitions at uncertain times, resulting in variable behavior. The variable behavior can be functionally correct, but still cause the data processing device to fail testing as the test outputs do not match a test program's expectations. Variability of device behavior can be reduced by applying a common test clock to all clock domains of the data processing device during testing. However, this may not accurately reflect the normal operating conditions of the data processing device, thereby reducing the accuracy of the test results. Therefore, a device and method for transferring data between clock domains of a device under test would be useful.